Computing the Entire Active Area / Power Consumption versus Delay Trade-oo Curve for Gate Sizing with a Piecewise Linear Simulator

| The gate sizing problem is the problem of nd-ing load drive capabilities for all gates in a given Boolean network such, that a given delay limit is kept, and the necessary cost in terms of active area usage and / or power consumption is minimal. This paper describes a way to obtain the entire cost versus delay trade-oo curve of a combi-national logic circuit in an eecient way. Every point on the resulting curve is the global optimum of the corresponding gate sizing problem. The problem is solved by mapping it onto piecewise linear models in such a way, that a piece-wise linear (circuit) simulator can do the job. It is shown that this setup is very eecient, and can produce trade-oo curves for large circuits (thousands of gates) in a few minutes. Benchmark results for the entire set of MCNC '91 two-level examples are given.